DocumentCode
3278430
Title
Formal verification of a pipelined processor with new memory hierarchy using a commercial model checker
Author
Nakamura, Hiroshi ; Arai, Takanori ; Fujita, Masahiro
Author_Institution
Res. Center for Adv. Sci. & Technol., Univ. of Tokyo, Japan
fYear
2002
fDate
16-18 Dec. 2002
Firstpage
321
Lastpage
324
Abstract
Recently, model checkers have become commercially available. To investigate their ability, Solidify is selected as the representative of them and applied to a verification of a new processor. The processor adopts new memory hierarchy and new instructions. Its instruction issue is pipelined and in-order. Our experiment reveals that Solidify can verify the processor but drastic abstraction is indispensable for successful verification. The experimental results also suggest that it is quite hard to verify more complex out-of-order issue processors without very drastic and efficient abstraction. Through the experience, we also recognize the benefit of fully automatic verification. However, we suffer from the invariant problems. Experience is still important for this problem.
Keywords
circuit analysis computing; formal verification; hardware description languages; microprocessor chips; pipeline processing; Solidify; abstraction; complex out-of-order issue processors; formal verification; fully automatic verification; invariant problems; memory hierarchy; model checkers; new processor verification; pipelined processor; Circuits; Computational modeling; Computer architecture; Electronic mail; Engines; Formal verification; Hardware design languages; Large-scale systems; Memory architecture; Solid modeling;
fLanguage
English
Publisher
ieee
Conference_Titel
Dependable Computing, 2002. Proceedings. 2002 Pacific Rim International Symposium on
Print_ISBN
0-7695-1852-4
Type
conf
DOI
10.1109/PRDC.2002.1185653
Filename
1185653
Link To Document