Exploiting the use of VHDL specifications in the AGENDA high-level synthesis environment

Recently, the AGENDA formal framework to perform high-level synthesis using attribute grammars has been presented, its main advantages being modularity and declarative notation in the development of EDA environments. To integrate this framework with modern optimization and technology mapping tools, compliance with the corresponding design entry method is needed. This paper gives a brief overview of AGENDA, focuses on different VHDL coding styles that have been adopted to describe the results of high-level synthesis and attempts comparisons between them. As it has been experimentally tested, the efficiency of the final design can be doubled by incorporation of more suitable coding styles. Such results can be proven very valuable in making VHDL an effective tool for tomorrow´s designers