Design for enhancing reliability of LD chip in a 10Gps optoelectronic package

The laser diode (LD) is a key component in optoelectronic packages like transmitters and transceivers. The performance and reliability of the LD will affect the functionality of the whole package. Stress in the active area of the LD has been observed to impact the operating characteristics of the device and operating life time. Therefore, it is important to reduce the stress in the LD to enhance the package reliability, especially for junction-down assembly, where higher stress exists. In this paper, a procedure is established to evaluate the impact of design variables on the stress level in the active area of the LD using FEA. The chip carrier material and thickness have been identified as critical parameters through virtual DOE. Design optimization is then performed to minimize the stress for the j-down configuration. Our study shows that by selecting proper materials and design scheme, the stress in the LD for j-down assembly can be less than that for conventional j-up assembly. Hence the performance and reliability of the new package can be maintained.