Register allocation with simultaneous BIST intrusion

We present an algorithm for register allocation of self-testable data paths, which have some test registers. Classical approaches synthesizing minimum area data paths and then adding minimum number of test registers to it do not lead to data paths with minimum global area. Testability consideration during synthesis makes design search more efficient and hence can possibly find self-testable data paths with minimum area. We present a model to evaluate the testability of data paths that is used when register allocation is being done. Moreover, we propose some heuristics that guide the design space search during allocation, to save exploration time. Each allocation decision is made according to testability and area increments that the alternatives for allocation produce, so that alternatives increasing area are only chosen when the testability gain is worth it