Verification of real time controllers against timing diagram specifications using constraint logic programming

Given a pseudo-synchronous (sampled input) finite-state machine (FSM) implementation of a real-time controller and a specification in the form of timing diagrams (TDs), the question we wish to answer is whether the controller satisfies the specification. The method we propose uses constraint logic programming (CLP) based on relational interval arithmetic (RIA) and domain narrowing. The controller FSM is fed with input sequences derived from the timing assumptions on the inputs as stated in the specification, and its outputs are verified against the required timing of the specification (the commit constraints). Since timing constraints in TD specifications usually involve intervals of possible values, there may be many input sequences satisfying the assumptions. We consider all possible input sequences in one symbolic execution of the machine derived from the TD and the controller by formulating the execution of the machine as consistency checking of a constraint system. The number of constraints checked is linear with the sum of the lengths of the intervals of the assumption constraints in the specification. It was implemented in CLP(BNR) Prolog