A new approach to AND/OR/EXOR factorization for regular arrays

Author

Song, Ning ; Perkowski, Marek

Author_Institution

Dept. of Electr. Eng., Portland State Univ., OR, USA

Volume

1

fYear

1998

fDate

25-27 Aug 1998

Firstpage

269

Abstract

The proposed factorization methods for regular arrays of two-input cells have several important advantages over the existing logic representations and methodologies. (1) The logic representation and design implementation are consistent. (2) The stages of logic synthesis and physical design are effectively merged into a single stage. (3) The structure of the mapping solution is a regular rectangle. (4) Since the connections are mainly between neighboring cells, the wire delay is reduced compared to other design methods. (5) Since the structure is regular, the creation of the high-performance tools is significantly easier. (6) The methods can be applied to fine-grain FPGA design, standard cell, gate matrix layout and sub-micron technologies

Keywords

logic arrays; logic design; AND/OR/EXOR factorization; design implementation; fine-grain FPGA design; gate matrix layout technologies; high-performance tools; logic representation; logic synthesis; mapping solution structure; neighboring cell connections; physical design; regular arrays; regular rectangle; standard cell technologies; sub-micron technologies; two-input cells; wire delay; Delay effects; Design methodology; Field programmable gate arrays; Input variables; Logic arrays; Logic design; Minimization methods; Programmable logic arrays; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Euromicro Conference, 1998. Proceedings. 24th

Conference_Location

Vasteras

ISSN

1089-6503

Print_ISBN

0-8186-8646-4

Type

conf

DOI

10.1109/EURMIC.1998.711810

Filename

711810