The development of enhanced wafer level packaging

In this paper, one of the wafer level chip scale packaging (WL-CSP) patents issued by ERSO/ITRI, the double elastomer wafer level package, is implemented on the test vehicle of Rambus DRAM to demonstrate the applicability and reliability of WL-CSP for high performance devices. In this design, both thermal and electrical performance enhancements are considered. To demonstrate the reliability of the enhanced WL-CSP, both the component- and board-level criteria are studied, which includes the evaluation of UBM (under bump metallurgy) by adopting low cost electroless and electroplating Ni/Au processes. Results show that the developed thermally and electrically enhanced WL-CSP can pass the reliability tests of pre-con, TC (temperature cycling), PCT (pressure cooker test), and HST (humidity storage test) at component-level and PCT at board-level. Although the board-level TC is on-going, which targets 1000 cycles, early studies of typical FMA are presented here. Moreover, preliminary studies of improving the board-level TC reliability are also included in the paper.