Title :
Surfing interconnect
Author :
Greenstreet, Mark R. ; Ren, Jihong
Author_Institution :
Dept. of Comput. Sci., British Columbia Univ., Vancouver, BC
Abstract :
We present a novel approach to long-wire signalling. We use the traditional division of long wires into buffered segments, but the delay of each buffer is modulated by signals derived from a timing chain. This creates a circuit element whose timing behaviour is between that of an inverter and that of a latch. We call these "soft latches". We demonstrate the advantages of our approach by comparing it with synchronous and asynchronous interconnect pipelining. We present results from HSPICE simulations to evaluate the robustness of our circuits
Keywords :
flip-flops; integrated circuit interconnections; logic design; HSPICE simulations; asynchronous interconnect pipelining; circuit element; integrated circuit interconnections; long-wire signalling; soft latches; synchronous interconnect pipelining; timing behaviour; Clocks; Delay; Integrated circuit interconnections; Inverters; Latches; Pipeline processing; Power system interconnection; System-on-a-chip; Timing; Wire;
Conference_Titel :
Asynchronous Circuits and Systems, 2006. 12th IEEE International Symposium on
Conference_Location :
Grenoble
Print_ISBN :
0-7695-2498-2
DOI :
10.1109/ASYNC.2006.28
