Estimation and consideration of interconnection delays during high-level synthesis

In deep submicron designs the interconnection delays will have a strong influence on the timing behavior of the circuits. Traditional high-level synthesis systems, however, do not consider interconnection delays. We propose techniques that address this problem by estimating the delay and area cost of the interconnections during the high-level synthesis process. The interconnection delays are used to guide the scheduling, allocation, and binding, which are performed in a single step in our approach. The experimental results show the importance of taking the effects of the interconnections into account