Title :
Modified derivative superposition method for linearizing FET low noise amplifiers
Author :
Aparin, Vladimir ; Larson, Lawrence E.
Author_Institution :
QUALCOMM Inc., San Diego, CA, USA
Abstract :
The degrading effect of the circuit reactances on the maximum IIP3 (third order input intercept point) in the conventional derivative superposition (DS) method is explained using Volterra series analysis. The effect on the NF of the subthreshold biasing of one of the FETs in the DS method is also explained. A modified DS method is proposed to increase the maximum IIP3 at RF. It was used in a 0.25 μm Si CMOS LNA designed for cellular CDMA receivers. The LNA achieved +17.2 dBm IIP3 with 15.5 dB gain, 1.6 dB NF and 9 mA at 2.6 V power consumption.
Keywords :
CMOS analogue integrated circuits; Volterra series; cellular radio; code division multiple access; electric reactance; field effect transistor circuits; integrated circuit design; integrated circuit noise; linearisation techniques; network analysis; power consumption; radiofrequency amplifiers; 0.25 micron; 1.6 dB; 15.5 dB; 2.6 V; 9 mA; FET low noise amplifier linearization; IIP3; Si; Volterra series analysis; cellular CDMA receivers; circuit reactance; modified derivative superposition method; noise figure; power consumption; third order input intercept point; Circuit noise; Degradation; FETs; Low-noise amplifiers; Multiaccess communication; Noise measurement; Predictive models; Radio frequency; Radiofrequency amplifiers; Voltage;
Conference_Titel :
Radio Frequency Integrated Circuits (RFIC) Symposium, 2004. Digest of Papers. 2004 IEEE
Print_ISBN :
0-7803-8333-8
DOI :
10.1109/RFIC.2004.1320540
