DocumentCode :
3278938
Title :
Synthesising heterogeneously encoded systems
Author :
Toms, W.B. ; Edwards, D.A. ; Bardsley, A.
Author_Institution :
Sch. of Comput. Sci., Manchester Univ.
fYear :
2006
fDate :
13-15 March 2006
Lastpage :
149
Abstract :
Self-timed datapaths require their data to be encoded in a delay-insensitive manner. The dual-rail encoding is commonly used, but more complex codes offer the possibility of better energy efficiency or fewer wires-per-bit. However, these advantages are often negated by datapath manipulations within large systems that require code-groups to be split and reformed. These overheads may be reduced by heterogeneously encoding circuits based on the datapath requirements within the circuits. In this paper, such an approach is evaluated within the Balsa asynchronous synthesis system. Techniques for synthesising arbitrary m-of-n encodings for datapath components are presented. These implementations allow each channel within a handshake circuit to be assigned an individual encoding. An automated encoding mechanism is described which analyses the datapath requirements of Balsa circuits and assigns codes to channels based on the interaction between sections of datapaths. The performance of the heterogeneous approach is evaluated on two microprocessor implementations
Keywords :
asynchronous circuits; encoding; high level synthesis; logic design; Balsa asynchronous synthesis system; automated encoding mechanism; datapath components; handshake circuit; heterogeneously encoded systems; m-of-n encodings; microprocessor implementations; Circuit synthesis; Computer science; Data analysis; Delay; Energy efficiency; Microprocessors; Protocols; Timing; Very large scale integration; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Asynchronous Circuits and Systems, 2006. 12th IEEE International Symposium on
Conference_Location :
Grenoble
ISSN :
1522-8681
Print_ISBN :
0-7695-2498-2
Type :
conf
DOI :
10.1109/ASYNC.2006.29
Filename :
1595697
Link To Document :
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