DocumentCode :
3279365
Title :
Process development for ultra low loop reverse wire bonding on copper bond pad metallization
Author :
Ganesh, V.P. ; Sivakumar, Mohandass
Author_Institution :
A-Star Inst. Of Microelectron., Singapore, Singapore
fYear :
2002
fDate :
10-12 Dec. 2002
Firstpage :
356
Lastpage :
360
Abstract :
Wire bond technology will continue to evolve and remain to be the dominant interconnect for low cost products until flip chip costs become favorable. To keep in pace with thinner high density packaging and copper (Cu) metallized wafer interconnect trends, wire bonding is moving towards fine pitch, ultra low loop application and bonding on alternate metal cap metallization. In this research work the objective is to develop ultra low loop reverse wire bonding method on capped Copper bond pad metallization. Test chips are fabricated with Cu bond pad metallization, Electroless Nickel Immersion Gold (ENIG) plating is done and these chips are reverse wire bonded with 25.4μm gold (Au) wire. Second bond parameters and looping parameters are optimized to achieve desired second bond pull and minimum loop height ensuring enough die edge to wire clearance during wire bonding. By this novel method ultra low loop height of 30 μm using 25.4 μm gold wire, eliminating gold stud-bumping process on Cu metallized bond pad is achieved. Electroless Nickel immersion gold process, parameter optimization for looping, second bond, wedge pull data, failure mode and Auger Electron Spectroscopy (AES) analysis on the surface of bond pads are discussed in detail in this paper. Thus this work gives an ideal solution for Cu metallized chip packaging combined with the lowest ultra loops possible for thinner packages.
Keywords :
Auger electron spectra; copper; electroless deposited coatings; failure analysis; gold; integrated circuit metallisation; lead bonding; nickel; optimisation; packaging; 25.4 micron; 30 micron; AES analysis; Au-Ni-Au-Cu; Cu metallized wafer interconnect; ENIG; bond parameters; capped Cu bond pad metallization; electroless Ni immersion Au plating; electroless nickel immersion gold; electronic packaging; failure mode analysis; fine pitch application; looping parameters; low loop reverse wire bonding; process development; Copper; Costs; Flip chip; Gold; Metallization; Nickel; Packaging; Testing; Wafer bonding; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics Packaging Technology Conference, 2002. 4th
Print_ISBN :
0-7803-7435-5
Type :
conf
DOI :
10.1109/EPTC.2002.1185697
Filename :
1185697
Link To Document :
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