TDC-based frequency synthesizer for wireless applications

We analyze phase noise performance and further discuss details of an all-digital PLL that is used in a commercial 130 nm CMOS single-chip Bluetooth radio. The frequency synthesizer uses a digitally controlled oscillator with a digital loop filter and a time-to-digital converter that acts as a phase/frequency detector. When implemented in a deep-submicron CMOS, the presented architecture appears more advantageous over conventional charge-pump-based PLL, since it contains only two intrinsic phase noise sources and it does not rely on the fine voltage resolution of analog circuits. The measured close-in phase noise of -86.2 dBc/Hz and the rms phase error of 0.9° are adequate also for GSM applications.