DocumentCode
3279519
Title
Parameters design of 1.25GHz low jitter charge pump PLL
Author
Xu, Xiaoliang ; Liu, Huihua ; Tan, Weifeng
Author_Institution
Res. Inst. of Electron. Sci. & Technol., Univ. of Electron. Sci. & Technol. of China, Chengdu, China
fYear
2011
fDate
15-17 April 2011
Firstpage
3418
Lastpage
3421
Abstract
Third-order charge-pump phase-locked circuit is simulated, system parameters ware designed by the perspective of jitter of the system, and the phase noise, settling time, and other aspects of system parameters; The result is that the jitter of PLL is 1.5 ps with phase noise 108 dBc/Hz@1MHz, and the lock time is 4 us. This idea of the design can be applied to design variety of charge-pump PLL.
Keywords
jitter; phase locked loops; phase noise; frequency 1.25 GHz; lock time; low-jitter charge pump PLL; parameters design; phase noise; settling time; third-order charge-pump phase-locked circuit; Charge pumps; Jitter; Phase frequency detector; Phase locked loops; Phase noise; Radio frequency; Voltage-controlled oscillators; Charge Pump PLL; Jitter; Phase noise; System-level design;
fLanguage
English
Publisher
ieee
Conference_Titel
Electric Information and Control Engineering (ICEICE), 2011 International Conference on
Conference_Location
Wuhan
Print_ISBN
978-1-4244-8036-4
Type
conf
DOI
10.1109/ICEICE.2011.5777576
Filename
5777576
Link To Document