A 10 Gbit/s switch matrix MMIC using InP HEMTs with a logic-level-independent interface

Author

Kamitsuna, Hideki ; Kitabayashi, Hiroto ; Matsuzaki, Hideaki ; Tokumitsu, Masami ; Muraguchi, Masahiro

Author_Institution

NTT Photonics Labs., NTT Corp., Kanagawa, Japan

fYear

2004

fDate

6-8 June 2004

Firstpage

325

Lastpage

328

Abstract

An InP HEMT with a low on-resistance × off-capacitance (Ron × Coff) product enables us to configure a dc-to-over-10 GHz switch without using a shunt FET. The series FET configuration makes possible control-voltage-polarity independence, and offers a logic-level-independent interface. A 2×2 switch matrix MMIC yields an insertion loss of less than 1.16 dB and an isolation of more than 21.2 dB below 10 GHz. The MMIC also achieves error-free switch matrix operation up to 12.5 Gbit/s, using either a source coupled FET logic SCFL (1 V_p-p, dc offset: -0.5 V) or low voltage differential signalling LVDS (0.3 V_p-p, dc offset: +1.2 V) level.

Keywords

HEMT integrated circuits; III-V semiconductors; field effect MMIC; field effect transistor switches; indium compounds; optical fibre LAN; 10 Gbit/s; 12.5 Gbit/s; Ethernet switches; HEMT; InP; LVDS level; MMIC switch matrix; SCFL level; control-voltage-polarity independence; error-free switch matrix operation; insertion loss; logic-level-independent interface; low-voltage differential signaling; series FET configuration; source coupled FET logic; wideband switch; Baseband; Ethernet networks; FETs; HEMTs; Indium phosphide; Insertion loss; MMICs; MODFETs; Switches; Wideband;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Frequency Integrated Circuits (RFIC) Symposium, 2004. Digest of Papers. 2004 IEEE

ISSN

1529-2517

Print_ISBN

0-7803-8333-8

Type

conf

DOI

10.1109/RFIC.2004.1320610

Filename

1320610