Low-voltage process-adaptive logic and memory arrays for ultralow-power sensor nodes

We propose process variation tolerant circuit techniques for robust digital subthreshold logic and memory for ultralow power sensor nodes. Based on the concepts developed in this paper, we present an 8×8 process-tolerant FIR filter, working in both superthreshold and subthreshold regions featuring adaptive ß-ratio modulation and integrated level converters. Ultra-dynamic voltage scaling (UVDS) enables the filter operation at 85 mV consuming 40 nW. For memory applications, we propose Schmitt Trigger based SRAM bitcell exhibiting built-in process variation tolerance. Functional SRAM with the proposed memory bitcell is demonstrated at 160 mV in 0.13 ¿m CMOS technology.