DocumentCode
3280399
Title
Early screening method of chip-package interaction for multi-layer Cu/low-k structure using high load indentation test
Author
Usami, Takashi ; Nakamura, T. ; Yashima, Iwao
Author_Institution
Renesas Electron. Corp., Yamagata, Japan
fYear
2013
fDate
13-15 June 2013
Firstpage
1
Lastpage
3
Abstract
We have developed High Load Indentation (HiLI) test as a novel early screening method of Chip-Package Interaction (CPI) for multi-layer Cu/Low-k interconnects structure with bumps. In this study, by using HiLI test, we evaluated a lower fracture toughness SiCOH (Low-k), a thicker under bump metallization (UBM) and a plasma-damaged polyimide (PI) around these bumps, whose white bump failures relatively tend to occur compared to the standard structure. We found that both these in-situ load profiles and observations after the test corresponded with these white bump failures. In addition, we compared between a polished bump structure and an un-polished bump one by the test.
Keywords
chip scale packaging; copper; fracture toughness testing; indentation; integrated circuit interconnections; metallisation; multilayers; silicon compounds; CPI; Cu; HiLI test; SiCOH; UBM; chip-package interaction; fracture toughness; high load indentation test; low-k interconnects structure; low-k structure; multilayer Cu; plasma-damaged polyimide; polished bump structure; screening method; under bump metallization; white bump failures; Optical films; Optical microscopy; Polyimides; Scanning electron microscopy; Standards;
fLanguage
English
Publisher
ieee
Conference_Titel
Interconnect Technology Conference (IITC), 2013 IEEE International
Conference_Location
Kyoto
Print_ISBN
978-1-4799-0438-9
Type
conf
DOI
10.1109/IITC.2013.6615568
Filename
6615568
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