Fully pipelined VLSI architecture of a real-time block-based object detector for intelligent video surveillance systems

This paper presents a VLSI architecture of real-time object detection design for the intelligent video surveillance systems. In order to achieve the targets of high performance, low cost, and high accuracy, an efficient block-based background subtraction (BBS) algorithm had been created for VLSI implementation. It included a background model, a luminance generator, and a block difference model. The warning signals in the intelligent video surveillance systems will be triggered once more than a threshold number of blocks are marked as object discovered blocks. The VLSI architecture of this work contained 4.6-K gate counts and consumed 2.05 mW when it operated at 100 MHz processing rate by using a TSMC 0.18 um CMOS process. Compared with previous low-complexity designs, this work had the benefits of lower cost, higher performance and higher accuracy.