Title :
Fabrication and electrical characterization of 5×50um through silicon vias for 3D integration
Author :
Bhushan, Bharat ; Minrui Yu ; Dukovic, John ; Wong, Loke Yuen ; Kitowski, Aksel ; Mun Kvu Park ; Hua, Jingyu ; Bolagond, Shwetha ; Chan, Anthony C.-T ; Toh, Chin Hock ; Sundarrajan, Aditya ; Kumar, Narendra ; Ramaswami, Sesh
Author_Institution :
Silicon Syst. Group, Appl. Mater. Inc., Singapore, Singapore
Abstract :
We present fabrication, electrical characterization, and metrology analysis results of 5×50um TSVs for 3D integration. Specifically, electrical performance of blind TSVs is evaluated by capacitance-voltage (CV) and current-voltage (IV) measurements. Important electrical parameters such as oxide capacitance, minimum TSV capacitance, leakage current, and breakdown voltage are extracted and show good results. The capacitance values also closely match model predictions. The electrical testing data are further verified with a variety of materials analysis techniques.
Keywords :
capacitance; integrated circuit interconnections; leakage currents; three-dimensional integrated circuits; 3D integration; breakdown voltage; capacitance-voltage measurements; current-voltage measurements; electrical testing data; leakage current; metrology analysis; minimum TSV capacitance; oxide capacitance; through silicon vias fabrication; Capacitance; Capacitance measurement; Current measurement; Fabrication; Silicon; Three-dimensional displays; Through-silicon vias;
Conference_Titel :
Interconnect Technology Conference (IITC), 2013 IEEE International
Conference_Location :
Kyoto
Print_ISBN :
978-1-4799-0438-9
DOI :
10.1109/IITC.2013.6615579
