A verification concept for microcontroller peripheral development and system integration

In microcontroller product development, core-based design is common practice. Standard peripherals are provided as library elements to decrease design time. With increasing system complexity, verification effort is often higher than design effort. Thus, soft-IPs should not only consist of synthesizable models and documentation, but in addition they should support verification of system-level integration. A testbench concept that supports reuse of testbench elements at the module- and system-level is proposed to reduce testbench development effort. Testbench elements are command driven VHDL behavioral models that can control each other through a common communication infrastructure. At module-level, testbench elements can be controlled by command files and at system-level by the assembler program, i.e. by the CPU