A 0.25 μm CMOS OPLL transmitter IC for GSM and DCS

Author

Su, Peng-Un ; Hsu, Chun-Ming

Author_Institution

SoC Technol. Center, Ind. Technol. Res. Inst., Hsin Chu, Taiwan

fYear

2004

fDate

6-8 June 2004

Firstpage

435

Lastpage

438

Abstract

A single chip CMOS GSM/DCS dual-band offset-PLL transmitter is presented in this paper. This chip includes a quadrature modulator and an offset-PLL (OPLL) modulation loop. Except for the loop filter and the high-power voltage controlled oscillator (TX VCO), everything is integrated into this chip to form a dual-band transmitter. This transmitter IC is fabricated in 0.25 μm CMOS process. The current consumption without TX VCO is about 23 mA under 2.7 V power supply for both bands. The measured rms and peak phase errors for GMSK modulated signals are about 1° and 2.4°, respectively. The measurements show comparable performance to its BiCMOS counterparts.

Keywords

CMOS integrated circuits; cellular radio; error analysis; minimum shift keying; phase locked loops; quadrature amplitude modulation; radiofrequency filters; radiofrequency integrated circuits; voltage-controlled oscillators; 0.25 micron; 2.7 V; 23 mA; CMOS OPLL transmitter IC; CMOS process; DCS; GMSK modulated signals; GSM; TX VCO; current consumption; high-power voltage controlled oscillator; loop filter; offset-PLL modulation loop; peak phase errors; power supply; quadrature modulator; rms phase errors; single chip CMOS GSM/DCS dual-band offset-PLL transmitter; transmitter IC; CMOS integrated circuits; CMOS process; Distributed control; Dual band; Filters; GSM; Phase measurement; Power supplies; Transmitters; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Frequency Integrated Circuits (RFIC) Symposium, 2004. Digest of Papers. 2004 IEEE

ISSN

1529-2517

Print_ISBN

0-7803-8333-8

Type

conf

DOI

10.1109/RFIC.2004.1320645

Filename

1320645