Title :
Restructuring wafers for maximum yield and some applications of WSI
Author_Institution :
Dept. of Comput. Sci. & Eng., Southern Methodist Univ., Dallas, TX, USA
Abstract :
The paper studies the problem of restructuring two dimensional wafers in the presence of faults. It constructs arrays of size as much as the size of the original faulty wafer. Obviously this is done at the cost of increased load factor. Later it shows how to construct small FFT machines on a two dimensional wafer. The FFT machines are constructed by embedding a butterfly graph in a two dimensional array in such a fashion that all the I/O nodes of a FFT graph are restricted to the periphery nodes of the mesh. It also minimizes the maximum wire length which is an important cost factor in such wafer scale designs
Keywords :
VLSI; fault tolerant computing; parallel algorithms; redundancy; systolic arrays; FFT graph; FFT machines; I/O nodes; WSI; butterfly graph; faulty wafer; load factor; maximum yield; periphery nodes; two dimensional array; two dimensional wafer; two dimensional wafers; wire length minimisation; Application software; Chip scale packaging; Circuit faults; Computer science; Costs; Power system interconnection; Very large scale integration; Wafer scale integration; Wire; Wiring;
Conference_Titel :
Parallel and Distributed Processing, 1990. Proceedings of the Second IEEE Symposium on
Conference_Location :
Dallas, TX
Print_ISBN :
0-8186-2087-0
DOI :
10.1109/SPDP.1990.143638