A sigma-delta based PLL for non-sinusoidal waveforms

The authors describe a phase-locked loop architecture for the locking of nonsinusoidal waveforms. It is based on the generation of the locking signal by means of a proper waveform synthesizer. The free-running frequency of the synthesizer is dynamically adjusted to ensure a suitable lock range. The system has been functionally analyzed and simulated, and its feasibility has been demonstrated. The lock range can extend over more than one decade. The system is suited to implementation using an oversampling approach. The reference waveform is generated with the direct-digital synthesis technique, which obtains the digital representation of the required locking signal by means of a proper ROM. This is converted into a sigma-delta flow by a digital sigma-delta modulator, and is then multiplied by the sigma-delta flow which represents the input signal. The filters and the processing circuits included in the system were realized with digital techniques