3281862

Multi-level Logic Optimization By Implication Analysis

Kunz, Wolfgang

1994

6-10 Nov 1994

6

13

Automatic logic units; Circuit synthesis; Circuit testing; Combinational circuits; Cost function; Energy consumption; Fault tolerance; Integrated circuit synthesis; Logic circuits; Minimization methods;

English

ieee

Computer-Aided Design, 1994., IEEE/ACM International Conference on

1063-6757

0-8186-3010-8

conf

10.1109/ICCAD.1994.629735

629735