A performance optimization tool for performance-driven micro-cell generation in sea-of-gates arrays

Author

LLopis, R. Peset ; Kerkhoff, H.G.

Author_Institution

MESA Res. Inst., Twente Univ., Enschede, Netherlands

Volume

6

fYear

1992

fDate

10-13 May 1992

Firstpage

2993

Abstract

A performance-driven microcell compiler for sea-of-gates arrays is proposed. This compiler is responsible for the generation of the layout of small logical cells in a semicustom environment. One part of this compiler, the topology generator, is described in more detail. The performance optimization methods in the literature have been analyzed, together with their application to the topology generator. This has resulted in a set of 12 performance optimization heuristics. The influence of each heuristic on the performance parameters has been studied by circuit simulations and by qualitatively considering capacitive and resistive effects. Several performance optimizations have been carried out, demonstrating that it is possible to optimize microcells for different performance parameters

Keywords

application specific integrated circuits; cellular arrays; circuit layout CAD; logic CAD; logic arrays; network topology; IC layout; SOG arrays; circuit simulations; logical cells; microcell compiler; performance optimization heuristics; performance optimization tool; performance-driven micro-cell generation; sea-of-gates arrays; semicustom environment; topology generator; Assembly; Circuits; Frequency; Logic; Noise shaping; Optimization methods; Power dissipation; Propagation delay; Topology; Working environment noise;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on

Conference_Location

San Diego, CA

Print_ISBN

0-7803-0593-0

Type

conf

DOI

10.1109/ISCAS.1992.230692

Filename

230692