Performance analysis of hierarchically structured multiple bus multiprocessor system

This paper presents a discrete time model of multiple level multiprocessor network with multiple buses at each level of hierarchy. The model describes each processing element´s (PE´s) behavior by means of a semi-Markov process. It takes as input the number of PEs, the number of memory modules (MMs), number of buses, the mean think time of a PE and the first and second moments of connection time. The model produces as output the bandwidth, the MM utilization PE utilization, average queue length, and average wait-time experienced by a PE while waiting to access a MM. An important design issue in the system under consideration is to optimize the communication network at each hierarchical level, meeting the overall communication requirements. The model developed is used to study the system behavior with different accessing patterns and design changes in the interconnection network at different hierarchical levels, enabling optimization of the design scheme