Title :
A high-density sea-of-gates architecture incorporating testability support
Author :
Koopman, R.J.H. ; Kerkhoff, H.G.
Author_Institution :
MESA Res. Inst., Twente Univ., Enschede, Netherlands
Abstract :
A new CMOS sea-of-gates master array architecture is presented. In this architecture, not only are routing considerations taken into account, but also performance considerations. These routing and performance arguments have both been used to determine the transistor gate widths. In doing so a high-density sea-of-gates architecture has been designed with good routing and performance characteristics. Special hardware was incorporated in the architecture to support design for testability
Keywords :
CMOS integrated circuits; cellular arrays; circuit layout; design for testability; integrated circuit testing; logic arrays; logic testing; network routing; CMOS; SOG; design for testability; high-density sea-of-gates architecture; master array architecture; routing; Circuits; Design for testability; Energy consumption; Hardware; Logic arrays; Logic design; MOSFETs; Routing; Testing; Wiring;
Conference_Titel :
Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0593-0
DOI :
10.1109/ISCAS.1992.230696
