Title :
Folding an array of transistors and contacts
Author :
Hu, T.C. ; Moerder, Karl Edwin ; Morgenthaler, J. David
Author_Institution :
Dept. of Comput. Sci. & Eng., California Univ., San Diego, CA, USA
Abstract :
The authors present a unified graph model for representing various layout and routing problems in VLSI design, such as programmable logic array (PLA) folding, gate matrix layout, and channel routing. They introduce an algorithm for folding a Weinberger array. This is a generalization of PLA folding, and is equivalent to channel routing. As a part of this algorithm, a graph labeling procedure is described which generalized the well-known topological sorting algorithm for directed acyclic graphs
Keywords :
VLSI; circuit layout CAD; directed graphs; logic CAD; logic arrays; network routing; network topology; IC layout; PLA folding; VLSI design; Weinberger array; channel routing; contacts; directed acyclic graphs; gate matrix layout; graph labeling procedure; programmable logic array; topological sorting algorithm; transistors; unified graph model; Circuits; Computer science; Design engineering; Labeling; Logic functions; Programmable logic arrays; Routing; Sorting; Very large scale integration; Wire;
Conference_Titel :
Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0593-0
DOI :
10.1109/ISCAS.1992.230698
