DocumentCode
32824
Title
Double-Shielded Interposer With Highly Doped Layers for High-Speed Signal Propagation
Author
Jun Li ; Xing-Chang Wei ; Xiao-Juan Wang ; Hui-Chun Yu ; De-Cao Yang ; Ran Hao ; Er-Ping Li
Author_Institution
Dept. of Inf. Sci. & Electron. Eng., Zhejiang Univ., Hangzhou, China
Volume
56
Issue
5
fYear
2014
fDate
Oct. 2014
Firstpage
1210
Lastpage
1217
Abstract
In this paper, we propose a novel double-shielded interposer design with two metal layers directly contacting to the silicon substrate surfaces for high-speed signal propagating along through silicon vias (TSVs). To enhance the shielding effects, shallow highly doped silicon is made on both sides of the silicon interposer forming ohmic contact between the metallization layer and silicon. The metallization layer is etched into meshed pattern to prevent delamination. Based on the imaging method, we derive the equivalent circuit model of the proposed double-shielded interposer, and the accuracy and efficiency of the equivalent circuit model is verified by full-wave method. The proposed design can concentrate the electromagnetic field around TSVs, so that it has a lower insertion loss than the conventional ground-signal (GS) structure without shielding. This is especially useful when the low-resistivity silicon is used for the interposer. Finally, some applied guidelines are proposed to strengthen the performance and simplify the silicon fabrication processes.
Keywords
electromagnetic fields; electromagnetic shielding; elemental semiconductors; equivalent circuits; ohmic contacts; semiconductor device metallisation; semiconductor doping; silicon; GS structure; Si; TSV; delamination; doped layers; double-shielded interposer design; electromagnetic field; equivalent circuit model; full-wave method; ground-signal structure; high-speed signal propagation; imaging method; low-resistivity silicon fabrication process; metal layers; metallization layer; ohmic contact; shallow doped silicon; shielding effect enhancement; silicon substrate surface; through silicon vias; Insertion loss; Integrated circuit modeling; Metallization; Silicon; Substrates; Through-silicon vias; Double-shielded interposer; highly doped silicon; insertion loss; meshed pattern; through silicon via (TSV);
fLanguage
English
Journal_Title
Electromagnetic Compatibility, IEEE Transactions on
Publisher
ieee
ISSN
0018-9375
Type
jour
DOI
10.1109/TEMC.2014.2307339
Filename
6766653
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