DocumentCode :
3282408
Title :
Wave-domino logic: timing analysis and applications
Author :
Lien, Wei-han ; Burleson, Wayne
Author_Institution :
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
Volume :
6
fYear :
1992
fDate :
10-13 May 1992
Firstpage :
2949
Abstract :
Wave-pipelining has been investigated extensively as a design method to increase clock frequencies of digital systems. The authors explore wave-pipelining of domino CMOS circuits because of their compact layouts and shorter delay time. A timing model and constraints are given for deriving the minimal period. Partitioning and restructuring of circuits for wave-pipelining are discussed. A test chip has been designed using a novel form of domino-logic to verify the concept
Keywords :
CMOS integrated circuits; integrated logic circuits; logic design; clock frequencies; clocking model; design method; digital systems; domino CMOS circuits; timing analysis; timing model; wave domino logic; wave-pipelining; CMOS logic circuits; Circuit testing; Clocks; Delay effects; Design methodology; Digital systems; Frequency; Propagation delay; Semiconductor device modeling; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0593-0
Type :
conf
DOI :
10.1109/ISCAS.1992.230703
Filename :
230703
Link To Document :
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