Resistant against power analysis for a fast parallel high-radix RSA algorithm

In this paper, an improved architecture for RSA coprocessor against power analysis was proposed, and power analysis (PA) for RSA coprocessor is studied in details. Firstly, the shadow technology was introduced into the RSA algorithm in order to increase the difficulty for differential power analysis (DPA) attack theoretically, secondly, there are not exist intermediate variable during the operation of the RSA algorithm, which could prevent the attacks from the simple power analysis (SPA), thirdly, a parallel architecture of RSA coprocessor was used to speed the RSA operation with three level pipelines. And theoretic analyses are given for the correctness of RSA-Shadow algorithm and the effectiveness against power analysis. The analyzed result showed that it would take about 498ms to encrypt 1024 bits plaintext under 5Mhz. Compared with previous works, our proposed architecture can decrease 21% clock counts, and its security was better greatly with a little cost, which would be meaningful for the physical security of a common crypto-system.