Modelling and optimising run-time reconfigurable systems

Author

Luk, Wayne ; Shirazi, Nabeel ; Cheung, Peter Y K

Author_Institution

Dept. of Comput., Imperial Coll. of Sci., Technol. & Med., London, UK

fYear

1996

fDate

17-19 Apr 1996

Firstpage

167

Lastpage

176

Abstract

We present a simple model for specifying and optimising designs which contain elements that can be reconfigured at run-time. In this model the control mechanism for reconfiguration can be implemented in many ways: by the user using multiplexers or other logic blocks, or by FPGAs which support dynamic partial reconfiguration. The model can be used for assessing trade-offs in run-time reconfigurable systems such as operation speed, design size, reconfiguration time and complexity of reconfiguration controllers; current work includes expressing the model in a framework which also captures layout information. Our approach is illustrated by various reconfigurable implementations for filtering and locating edges in images. The design tradeoffs of these implementations are being evaluated on a PCI platform, which contains a Xilinx 6216 device

Keywords

computational complexity; field programmable gate arrays; reconfigurable architectures; FPGAs; Xilinx 6216 device; complexity; control mechanism; dynamic partial reconfiguration; formal specification; logic blocks; multiplexers; reconfiguration controllers; run-time reconfigurable systems; Complexity theory;

fLanguage

English

Publisher

ieee

Conference_Titel

FPGAs for Custom Computing Machines, 1996. Proceedings. IEEE Symposium on

Conference_Location

Napa Valley, CA

Print_ISBN

0-8186-7548-9

Type

conf

DOI

10.1109/FPGA.1996.564815

Filename

564815