Title :
Does retiming affect redundancy in sequential circuits?
Author :
Das, Debesh K. ; Bhattacharya, Bhargab B.
Author_Institution :
Dept. of Comput. Sci. & Eng., Jadavpur Univ., Calcutta, India
Abstract :
Retiming is used to optimize logic and improve the speed of operation in sequential circuits keeping the circuit behavior unchanged. In this paper, we show with various examples that retiming affects redundancy of faults. It may change an operationally redundant fault to a partially one, and a combinationally redundant fault to an irredundant but sequentially untestable fault. Many novel transformations of combinational redundancy to sequential redundancies are also exemplified. Thus, retiming strongly influences test generation and design for testability techniques in sequential circuits
Keywords :
fault diagnosis; logic testing; redundancy; sequential circuits; timing; combinational redundancy; design for testability; fault; logic optimization; operation speed; retiming; sequential circuit; sequential redundancy; test generation; Circuit faults; Circuit testing; Clocks; Combinational circuits; Computer science; Electrical fault detection; Fault detection; Redundancy; Sequential analysis; Sequential circuits;
Conference_Titel :
VLSI Design, 1996. Proceedings., Ninth International Conference on
Conference_Location :
Bangalore
Print_ISBN :
0-8186-7228-5
DOI :
10.1109/ICVD.1996.489607
