A mixed-mode architecture for implementation of analog neural networks with digital programmability

In this paper we discuss a mixed-mode architecture for implementation of artificial neural networks (ANNs). This type of architecture is suitable for applications in the areas of nonlinear control and audio signal processing. Synapses are built with a switched-capacitor multiplying D/A converter (MDAC) and a pseudo 4Q analog multiplier. The multiplier inputs are voltages while its output is a current, The analog weight value is stored in a capacitor. The MDAC front-end is included with each synapse for D/A conversion and periodic on-chip refreshment of the capacitor charge. Neurons are built with MOS transistors exploiting the quadratic characteristics of the saturation region. A CMOS prototype chip was designed and fabricated for demonstration of the proposed architecture.