DocumentCode :
328356
Title :
Very-high-speed analog neural network LSI implementation using super self-aligned Si bipolar process technology
Author :
Aisawa, Shigeki ; Noguchi, Kazuhiro ; Koga, Masafunii ; Matsumoto, Takao ; Amemiya, Yoshiteru
Author_Institution :
NTT Transmission Syst. Labs., Kanagawa, Japan
Volume :
1
fYear :
1993
fDate :
25-29 Oct. 1993
Firstpage :
895
Abstract :
A very-high-speed ten-neuron analog neural network LSI chip is fabricated for the first time with super self-aligned Si bipolar process technology. The LSI consists of ten neurons and 100 electrically modifiable synaptic weights. The neural network nonlinear mapping function to solve the four-bit parity problem has been successfully demonstrated at 150 megapatterns/sec. The operation speed of this neural network is, to the best of the authors´ knowledge, the fastest yet reported.
Keywords :
analogue processing circuits; bipolar analogue integrated circuits; large scale integration; neural chips; very high speed integrated circuits; four-bit parity problem; nonlinear mapping function; super self-aligned Si bipolar process technology; ten-neuron analog neural network LSI chip; very-high-speed analog neural network LSI implementation; Circuits; Differential amplifiers; High speed optical techniques; Laboratories; Large scale integration; Neural networks; Neurons; Nonlinear optics; Optical signal processing; Signal design;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Neural Networks, 1993. IJCNN '93-Nagoya. Proceedings of 1993 International Joint Conference on
Print_ISBN :
0-7803-1421-2
Type :
conf
DOI :
10.1109/IJCNN.1993.714055
Filename :
714055
Link To Document :
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