Title :
A multilevel factorization technique for pass transistor logic
Author :
Jaekel, A. ; Jullien, G.A. ; Bandyopadhyay, S.
Author_Institution :
VLSI Res. Group, Windsor Univ., Ont., Canada
Abstract :
Pass transistor logic (PTL) networks have been used by many researchers to design fast, area efficient pipelined systems. Not much work has been done in the area of multilevel logic synthesis in PTL networks. In this paper, we have investigated the use of algebraic factorization techniques to synthesize multilevel PTL networks
Keywords :
circuit optimisation; logic CAD; minimisation of switching nets; multivalued logic circuits; algebraic factorization; area efficient pipelined systems; logic synthesis; multilevel factorization technique; pass transistor logic; Circuits; Costs; Input variables; Logic design; Minimization methods; Network synthesis; Very large scale integration;
Conference_Titel :
VLSI Design, 1996. Proceedings., Ninth International Conference on
Conference_Location :
Bangalore
Print_ISBN :
0-8186-7228-5
DOI :
10.1109/ICVD.1996.489630
