DocumentCode
3283680
Title
A multilevel factorization technique for pass transistor logic
Author
Jaekel, A. ; Jullien, G.A. ; Bandyopadhyay, S.
Author_Institution
VLSI Res. Group, Windsor Univ., Ont., Canada
fYear
1996
fDate
3-6 Jan 1996
Firstpage
339
Lastpage
340
Abstract
Pass transistor logic (PTL) networks have been used by many researchers to design fast, area efficient pipelined systems. Not much work has been done in the area of multilevel logic synthesis in PTL networks. In this paper, we have investigated the use of algebraic factorization techniques to synthesize multilevel PTL networks
Keywords
circuit optimisation; logic CAD; minimisation of switching nets; multivalued logic circuits; algebraic factorization; area efficient pipelined systems; logic synthesis; multilevel factorization technique; pass transistor logic; Circuits; Costs; Input variables; Logic design; Minimization methods; Network synthesis; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 1996. Proceedings., Ninth International Conference on
Conference_Location
Bangalore
ISSN
1063-9667
Print_ISBN
0-8186-7228-5
Type
conf
DOI
10.1109/ICVD.1996.489630
Filename
489630
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