• DocumentCode
    3283867
  • Title

    Vlsi Timing Simulation With Selective Dynamic Regionization

  • Author

    Yu, Meng-Lin ; Ackland, Bryan D.

  • fYear
    1994
  • fDate
    6-10 Nov 1994
  • Firstpage
    195
  • Lastpage
    199
  • Keywords
    Circuit simulation; Computational modeling; Discrete event simulation; Logic circuits; Read-write memory; SPICE; Switches; Timing; Very large scale integration; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer-Aided Design, 1994., IEEE/ACM International Conference on
  • ISSN
    1063-6757
  • Print_ISBN
    0-8186-3010-8
  • Type

    conf

  • DOI
    10.1109/ICCAD.1994.629765
  • Filename
    629765
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3283867