DocumentCode
3283971
Title
Improving accuracy in path delay fault coverage estimation
Author
Heragu, Keerthi ; Patel, Janak H. ; Agrawal, Vishwani D.
Author_Institution
Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
fYear
1996
fDate
3-6 Jan 1996
Firstpage
422
Lastpage
425
Abstract
A recently published method computes path delay fault coverage from the count of the number of path faults newly sensitized by a simulated vector pair. Such an estimate is pessimistic since several paths may share a set of lines. In this paper, we present a continuum of approximate methods, approaching exact fault simulation, for a tradeoff between accuracy and complexity. Higher accuracy is obtained at the expense of CPU time. We propose the use of flags corresponding to fixed-length path-segments. A flag indicates whether or not the segment has been included in a previously detected path fault. A path fault detected by a pair of vectors is counted as a new detection only if it includes at least one segment not included in any previously covered path. This gives us a pessimistic estimate of the number of newly detected faults by a simulated vector pair. When the numbers of fan-in and fan-out branches per gate are small, the method adds a modest overhead to good machine simulation provided the flagged path-segments are short. As the length of segments is increased, the accuracy approaches that of exact fault simulation. Results show that the estimates with small segment lengths are very close to actual fault coverages
Keywords
circuit analysis computing; combinational circuits; delays; fault diagnosis; graph theory; logic CAD; logic testing; CPU time; approximate methods; combinational paths; exact fault simulation; fan-in branches; fan-out branches; fault coverage estimation; fixed-length path-segments; flagged path-segments; path delay fault; segment lengths; simulated vector pair; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Delay estimation; Electrical fault detection; Estimation error; Fault detection; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 1996. Proceedings., Ninth International Conference on
Conference_Location
Bangalore
ISSN
1063-9667
Print_ISBN
0-8186-7228-5
Type
conf
DOI
10.1109/ICVD.1996.489646
Filename
489646
Link To Document