A high performance Low-Dropout regulator with a novel buffer

A novel buffer circuit for the Low-Dropout regulator (LDO) is presented to improve its transient behavior. The working principle of the buffer circuit is analyzed, and it is pointed out that the system´s bandwidth is extended by reducing the buffer´s output impedance. A local positive feedback in the proposed buffer reduces its output resistance so that the pole at the gate of the pass device is pushed into higher frequency without dissipating large quiescent current. Additionally, it also improves the respond speed of the system and reduces the quiescent power consumption. The simulation results based on the CSMC 0.6-μm CMOS process verify the correctness of the theoretical analysis and the feasibility of the proposed methods.