Title :
A radix-8 CMOS S/390 multiplier
Author :
Schwarz, Eric M. ; Averill, Robert M., III ; Sigal, Leon J.
Author_Institution :
IBM Corp., Poughkeepsie, NY, USA
Abstract :
The multiplier of a S/390 CMOS microprocessor is described. It is implemented in an aggressive static CMOS technology with a 0.20-μm effective channel length. The multiplier has been demonstrated in a single-image shared-memory multiprocessor at frequencies up to 400 MHz. The multiplier requires three machine cycles for a total latency of 7.5 ns, though the design can support a latency of 4.0 ns if the latches are removed. The design goal was to implement a versatile S/980 multiplier with reasonable performance at a very aggressive cycle time. The multiplier implements a radix-8 Booth algorithm and is capable of supporting S/390 floating-point and fixed-point multiplications, and also divisions and square roots. Logic design and physical design issues are discussed relating to the Booth decoding and counter tree implementations
Keywords :
CMOS digital integrated circuits; decoding; digital arithmetic; flip-flops; floating point arithmetic; logic design; microprocessor chips; multiplying circuits; performance evaluation; shared memory systems; 0.20 mum; 4.0 ns; 400 MHz; 7.5 ns; Booth decoding; S/390 CMOS microprocessor; aggressive static CMOS technology; counter tree implementation; cycle time; divisions; effective channel length; fixed-point multiplications; floating-point multiplications; latches; latency; logic design; multiplier; performance; physical design; radix-8 Booth algorithm; single-image shared-memory multiprocessor; square roots; CMOS technology; Cost function; Counting circuits; Decoding; Degradation; Delay; Fault tolerance; Logic design; Microprocessors; Tiles;
Conference_Titel :
Computer Arithmetic, 1997. Proceedings., 13th IEEE Symposium on
Conference_Location :
Asilomar, CA
Print_ISBN :
0-8186-7846-1
DOI :
10.1109/ARITH.1997.614873
