An ILP algorithm for voltage-island generation considering temperature in 3D-Ics

To reduce interconnect delay and improve chip performance, three-dimensional chip emerges with the rapid increasing of chip integration as well as chip power density. Therefore, the thermal optimization issue is one of the most serious challenges in 3D IC designs. With some low power technologies such as multi-supply voltage designs, the thermal management and the layout optimization becomes even more complex for 3D designs. In this paper, an ILP formulation is proposed to optimize not only the temperature distribution, but also power-network routing resources and the timing constraint. Experimental results show that, compared with original algorithm, our algorithm can obtain a lower chip temperature and the decrease of temperature exceeds performance overhead distinctly.