Clock Period Constrained Minimal Buffer Insertion In Clock Trees

fYear

1994

fDate

6-10 Nov 1994

Firstpage

219

Lastpage

223

Keywords

Algorithm design and analysis; Clocks; Delay effects; Frequency; Logic; Pins; Propagation delay; Routing; Synchronization; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer-Aided Design, 1994., IEEE/ACM International Conference on

ISSN

1063-6757

Print_ISBN

0-8186-3010-8

Type

conf

DOI

10.1109/ICCAD.1994.629769

Filename

629769

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