AES Embedded Hardware Implementation

The paper presents a parallel reconfigurable hardware implementation of the AES cryptographic algorithm developed for an embedded application. This new methodology directly maps a design described in a high level language, Handel-C, to FPGA platforms. The Handel-C approach narrows the gap between performance and flexibility, and thus, reduce the risk of translating a high level prototype into HDLs. It provides a high degree of flexibility from two viewpoints: the language level of abstraction and the hardware reconfiguration. Using Handel-C, we enhanced the performance of the designed unit by applying parallelism and reconfigurability. Our FPGA implementations show that superior performance can be achieved compared with software and hardware implementations counterparts. In particular, our design outperforms most of the other designs in speed. At the same time, the area cost for putting the AES algorithm on the same hardware core is also kept as low as possible.