An Fpga implementation of the HME self-synchronizing stream cipher for Enhanced security and performance

In this paper, we propose an FPGA implementation of a hybrid message-embedding (HME) self-synchronizing stream encryption based switched linear congruent pseudo-random generator. This encryption method is particularly attractive since it provides a low-cost security communication solution while increasing the throughput rate and decreasing the area of the FPGA circuit. This technique only requires addition, subtractions multiplication and word-shift operations and does not require the usually costly operations such as exponentiations. We propose an architecture using feedback logic, designed for small chip covered area and high speed performance. We show its feasibility through implementation which are presented and detailed by using Xilinx FPGA technology. This architecture employs only 162 slices with an achieved throughput equalling 659 Mbps by using a system clock with frequency up to 82. 3 7 MHz, a switching number of 4 and a number of key component equal to 2.