A GaAs 32-bit adder

Author

Beaumont-Smith, Andrew ; Burgess, Neil

Author_Institution

Dept. of Electr. & Electron. Eng., Adelaide Univ., SA, Australia

fYear

1997

fDate

6-9 Jul 1997

Firstpage

10

Lastpage

17

Abstract

Presents a new parallel GaAs 32-bit adder based on a combination of the Han-Carlson (1987) and Kowalczuk (1991) parallel adders. GaAs is particularly sensitive to loading, so our aim was to reduce the wire lengths and the fanout of each gate. Our architecture achieves this by significantly reducing the number of cells in the carry tree while not significantly reducing its speed. The delay of the adder fabricated in 0.6 μm MESFET GaAs technology was measured at 1.27 ns, with a power dissipation of 114 mW at 0.9 V. The area is 0.3 mm² with a maximum density of 8000 transistors/mm². The figure of merit is 0.21 μW/MHz·gate

Keywords

III-V semiconductors; MESFET integrated circuits; adders; field effect logic circuits; gallium arsenide; logic gates; 0.6 mum; 0.9 V; 1.27 ns; 114 mW; 32 bit; GaAs; GaAs 32-bit adder; MESFET GaAs technology; area; carry tree cells; delay; figure of merit; gate fanout; gate wire length; maximum transistor density; parallel adder; power dissipation; speed; Added delay; Adders; Gallium arsenide; Integrated circuit technology; Logic; MESFETs; Power dissipation; Silicon; Very large scale integration; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Arithmetic, 1997. Proceedings., 13th IEEE Symposium on

Conference_Location

Asilomar, CA

ISSN

1063-6889

Print_ISBN

0-8186-7846-1

Type

conf

DOI

10.1109/ARITH.1997.614874

Filename

614874