Systolic Array Based Architecture for Variable Block-Size Motion Estimation

A new systolic array based architecture is introduced for variable block-size motion estimation (VBSME). This comprises a 2D array structure for SAD value computation combined with a parallel adder tree and a SAD comparator unit. Parallel raster scan is applied leading to high processor utilization. The exhibits much simpler control and lower hardware cost compared with previous circuits and can handle flexible search ranges without any increase in silicon area. Resulting computational rates are suitable for high end video processing applications. This architecture can also be simply configured as other video compression standards usage. Silicon design studies, based on a 0.13 mum CMOS technology, indicate that circuits based on this approach are suitable for SDTV applications with search ranges of up to 32times32 and for HDTV applications with a search range of at least 16times16, with increased ranges achievable using lower dimension technologies.