System Level Modelling of Reconfigurable FFT Architecture for System-on-Chip Design

In the system-on-chip (SoC) era, the growing number of functionalities included on a single chip requires the development of new design methodologies to keep the design complexity under control. Intellectual property reuse has been commonly employed as a technique to address this problem, but a new system-level approach is needed to integrate IP-Reuse methodology in the design flow, in order to speed up the designer´s productivity. This paper aims to produce new high level IP models in SystemC for functional verification of IP integrations, incorporating both embedded custom reconfigurable and conventional IPs, which are optimised in terms of IP Core parameters. As a case study, a novel reconfigurable FFT architecture is presented and modelled in SystemC. Power, area and performance figures are presented as well.