DocumentCode

3284963

Title

Retiming With Non-zero Clock Skew, Variable Register, and Interconnect Delay

Author

Soyata, Tolga ; Friedman, Eby G.

fYear

1994

fDate

6-10 Nov 1994

Firstpage

234

Lastpage

241

Keywords

Buildings; Clocks; Delay effects; Design methodology; Frequency; Integrated circuit interconnections; Joining processes; Logic design; Registers; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer-Aided Design, 1994., IEEE/ACM International Conference on

ISSN

1063-6757

Print_ISBN

0-8186-3010-8

Type

conf

DOI

10.1109/ICCAD.1994.629771

Filename

629771