Title :
Retiming With Non-zero Clock Skew, Variable Register, and Interconnect Delay
Author :
Soyata, Tolga ; Friedman, Eby G.
Keywords :
Buildings; Clocks; Delay effects; Design methodology; Frequency; Integrated circuit interconnections; Joining processes; Logic design; Registers; Timing;
Conference_Titel :
Computer-Aided Design, 1994., IEEE/ACM International Conference on
Print_ISBN :
0-8186-3010-8
DOI :
10.1109/ICCAD.1994.629771
