A Hardware Preemptive Multitasking Mechanism Based on Scan-path Register Structure for FPGA-based Reconfigurable Systems

In this paper, we propose a hardware preemptive multitasking mechanism which uses scan-path register structure and allows identifying the total task´s register size for the FPGA-based reconfigurable systems. The main objective of this preemptive mechanism is to suspend hardware task having low priority, replace it by high-priority task and restart them at another time (and/or from another area of the FPGA in FPGA-based designs). The main advantages of the proposed method are that it provides an attractive way for context saving and restoring of a hardware task without freezing other tasks during pre-emption phases and a small area overhead. We show its feasibility by allowing us to design a simple computing example as well as the implementation of AES-128 encryption algorithm which are presented in and detailed on the Xilinx Virtex FPGA technology.