DocumentCode
3285276
Title
Topography Simulation for Wafer-scale Structural Analysis
Author
Lee, Jun-Gu ; Won, Taeyoung
fYear
2005
fDate
Dec. 7-9, 2005
Firstpage
382
Lastpage
383
Keywords
Analytical models; Computational modeling; Dielectrics; Etching; Level set; Mesh generation; Parasitic capacitance; Read only memory; Surface topography; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Device Research Symposium, 2005 International
Print_ISBN
1-4244-0083-X
Type
conf
DOI
10.1109/ISDRS.2005.1596146
Filename
1596146
Link To Document